Memory devices are very important in the art of digital electronics. Memory devices are used to store software programs and processed data. Write capable memory, such as random access memory, or RAM, is particularly important for storing data. In a Static RAM, or SRAM, device, data written to a memory cell can be stored indefinitely as long as power is supplied to the device. Further, the stored data can be changed by rewriting the cell. However, unlike dynamic RAM, or DRAM, the data value does not have to be periodically refreshed.
FIG. 1 illustrates a conventional SRAM cell 10 in schematic form. The SRAM cell 10 comprises six transistors and therefore is referred to as a 6T cell. In particular, the cell comprises pull-down NMOS field effect transistors (NFETs) 12 and 14, pull-up PMOS field effect transistors (PFETs) 16 and 18, and pass-gate NFETs 20 and 22. Transistor pairs 12 and 16 form a first inverter and transistor pairs 14 and 18 form a second inverter. The input of the first inverter (NFET 12 and PFET 16) is coupled to the output of the second inverter (NFET 14 and PFET 18). Similarly, the input of the second inverter (NFET 14 and PFET 18) is coupled to the output of the first inverter (NFET 12 and PFET 16). In this arrangement, a digital latch is formed. The digital latch, comprising NFET 12, PFET 16, NFET 14, and PFET 18, has two key nodes 24 and 26. The digital latch is electrically able to maintain either of two states. In one state, node 24 is high and node 26 is low. In the other state, node 24 is low and node 26 is high.
Pass-gate NFETs 20 and 22 are used to control access to the digital latch. Pass-gate NFETs 20 and 22 are controlled by a common signal, conveyed on a word line (WL) 28. When WL 28 is asserted, the pass-gate NFETs 20 and 22 are turned ON. In this state, a bit line (BL) 30 is coupled to node 24, and a bit line bar (BLB) or complementary bit line 32 is coupled to node 26. If the WL 28 assertion is due to a READ operation of the cell 10, then the BL 30 and BLB 32 signal lines will be coupled to a high impedance input stage of a bit line sense amplifier (not shown). This amplifier will be used to read the voltage state (high or low) of the BL 30 and BLB 32 signals to thereby determine the stored state of the cell 10. If the WL 28 assertion is due to a WRITE operation, then the BL 30 and BLB 32 signals will be driven to opposite voltages (Vdd and Vss) by a writing circuit (not shown). This will force the digital latch nodes 24 and 26 to the proper write state. When WL 28 is de-asserted, the pass-gate NFETs 20 and 22 are turned OFF, and the write state is held in the digital latch.
A large number of cells 10 can be designed into a memory array so that a large amount of data can be stored. However, there is a never-ending quest to integrate more circuitry onto a single integrated circuit. The goal of integrating entire systems on a chip has resulted in the motivation to include more memory capacity for those systems and, hence, to increase the density of the integrated circuit to include more memory cells in a given area on a chip.
One of the ways in which memory circuitry in general has become more dense is simply by reduction of the size of features (line widths and spaces) of elements making up the circuitry. By reducing these dimensions, SRAM cell density can be increased. However, reducing the width and spacing of features of memory cells, if carried to extremes, can reduce the electrical stability and, hence, manufacturability, of the memory cells.
Accordingly, it is desirable to provide a memory cell that can be scaled in size without a significant reduction in manufacturability. In addition, it is desirable to provide a method for manufacturing a scaled memory cell with desired performance properties. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.